This Partnership for Innovation project from Arizona State University is aimed at developing a new approach to digital system design in order to significantly reduce the power consumption and size of digital systems without reducing their speed of operation. If successful, the results of this research can be used to improve the energy efficiency of nearly every digital system, including desktop computers, laptops, tablets, cell phones and other handheld digital devices. This new approach employs threshold logic gates, which compute logic functions in a manner that is distinctly different from the way conventional logic gates operate. A threshold logic gate implements a complex logic function in a single primitive cell, which would otherwise require a network of many conventional logic gates. It is this absorption of logic into a single cell that is the reason for the reduction in power and size. A novel architecture for a threshold logic gate, called a differential threshold logic latch (DTLL), is proposed as the primitive logic cell.

DTLL cells are compatible with existing logic gates, and can be used to replace parts of a digital circuit to reduce its power and area and possibly improve its speed. The resulting circuit will be a hybrid, consisting of DTLL cells and conventional logic gates. A significant advantage of the proposed approach is that DTLL cells can be implemented as efficiently as standard cells, making it possible to integrate threshold logic technology with existing Application Specific Integrated Circuit (ASIC) design methodology. To enable the integration of threshold logic with conventional ASIC design requires the development of design infrastructure, which includes the design of a threshold cell library, and a host of algorithms and software tools that transform existing digital designs into hybrid designs. This project will build such an infrastructure.

The broader impacts of the project will be benefits to performance of mobile electronic applications such as smart phones, cameras, laptops, etc. These devices will benefit the most from a reduction in power consumption delivered as a result of this project. A fundamental advantage of the approach taken in this project to reducing power consumption is that the technology of threshold logic is compatible with existing logic. As a result, the proposed approach is fully compatible with existing industrial design methodology. No new fabrication technology will be required, and existing commercial back-end design tools (e.g., synthesis, optimization, placement and routing) can be used for the hybrid netlists.

Partners at the inception of the project: the knowledge enhancement partners (KEP): Lead institution: Arizona State University (Ira A. Fulton Schools of Engineering and School of Computing, Informatics and Decision Systems Engineering); and Small Businesses: Cactus Semiconductor Inc. and Everspin Inc. Other Partners--Large Businesses: Qualcomm and Texas Instruments.